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SAN JOSE, Calif.--(BUSINESS WIRE)--June 18, 2001--Today 0-In Design Automation, Inc., the leader in white-box verification technology, announced a collaboration to enable VERA®, Synopsys' (Nasdaq:SNPS) testbench automation tool, to react to structural coverage information in 0-In's CheckerWare library. Reactive testbenches improve verification efficacy by adapting their test generation in response to activity and coverage information from checkers that monitor internal design activity. Now VERA testbenches can be tailored for optimal design exercise as measured by the internal, white-box CheckerWare checkers and the CheckerWare monitors on interfaces.

OpenVera Initiative is Key to Cooperation

The OpenVera(TM) hardware verification language enables development of more verification products to solve difficult verification challenges. ``We were delighted when Synopsys introduced OpenVera as an open language available to the rest of the industry,'' commented 0-In CEO, Dr. L. Curtis Widdoes. ``Given the wide adoption of OpenVera as a hardware verification language and CheckerWare as an assertion method, linking these solutions is a natural step.''

    0-In Checkers and Monitors Provide Valuable Feedback on Design
    Activity

CheckerWare checkers map directly to data path and control structures in an RTL design. The checkers run in simulation and report any violations of the designer's assumptions. At the same time, 0-In checkers monitor design activity and report how well the simulation tests have exercised the RTL structures. Similarly, CheckerWare Monitors check for protocol violations and report how well the simulation tests have exercised possible transaction types on the interfaces.

``Since 0-In added structural coverage to our CheckerWare checkers and monitors six months ago, the coverage reports have been rapidly and enthusiastically embraced by our customers,'' reported Dr. Widdoes. ``We provide summary structural coverage reports at the end of a simulation test and report aggregate results across an entire regression suite. This provides very useful feedback on how well the simulation tests are exercising the interfaces and internal RTL structures of the design.''

    Structural Coverage Information Available to Simulation
    Testbenches

CheckerWare checkers and monitors provide structural coverage information in real time during simulations. ``Many of our advanced customers would like to use the internal, white-box coverage information to guide the tests they generate with their black-box verification environments,'' explained Dr. Widdoes. For example, if a 0-In checker detects that a networking channel FIFO is not being filled during a simulation, the VERA testbench tool can react by generating more packets targeting that particular channel.

VERA Users Can Leverage the Extensive CheckerWare Library

``VERA enables our customers to develop sophisticated testbench environments capable of generating a wide range of complex design activity,'' said Farhad Hayat, vice president of marketing, verification technology group at Synopsys. ``The Vera Open Source Initiative is enabling our customers to have access to a broad set of verification tools based on an open language. We are excited about the new integration between OpenVera and the 0-In CheckerWare library and believe verification engineers will benefit from the power of this combined solution.''

About 0-In

0-In Design Automation, Inc. (pronounced ``zero-in'') is a privately held electronic design automation (EDA) company providing functional verification products that help verify multi-million gate ASIC and SOC designs. 0-In was founded in 1996 and is based in San Jose, CA, with sales offices in Boxborough, MA and Austin, TX plus distribution in Japan through Pacific Design Inc. Leading-edge companies that have adopted 0-In tools and methodologies include AMD, Avaz Networks, Fujitsu, HP, Hitachi, Hughes, Lucent, National Semiconductor, Nortel, Sun, Tensilica and others. More information on 0-In is available at http://www.0-in.com

0-In(TM) and CheckerWare(TM) are trademarks of 0-In Design Automation, Inc.

     0-In Design Automation
     Steven D White, 408/487-3649
     swhite@0-in.com